1. Field of the Invention
This invention generally relates to computer-implemented methods and carrier mediums used to enhance lithographic processes, and more particularly, to computer-implemented methods and carrier mediums used generate a set of process parameter values for a lithography process and/or a list of potential causes of specification deviations resulting from a lithographic process.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Lithography processes may be used in a variety of applications. For instance, semiconductor device fabrication processes typically involve a number of lithography steps to form various features and multiple levels of a semiconductor device. In general, “lithography” may refer to a process in which a pattern is transferred onto a surface. As such, a lithography process used in the fabrication of a semiconductor device may refer to a process in which a pattern is transferred onto a wafer. In the fabrication of semiconductor devices, a lithography process may be conducted in multiple steps. For example, a lithography process may involve coating a wafer with a photoresist layer and subsequently transferring a patterned image from a reticle or mask to the photoresist material. In some cases, the process may include baking the wafer before and/or after the pattern transfer step such that residual solvent from the coating process may be removed and regions of the photoresist exposed and not exposed by the patterning process may be diffused, respectively. In any case, the process may include removing portions of the photoresist layer such that a pattern imaged from the reticle remains. Subsequently, the process may include etching underlying layers of the wafer to replicate the pattern formed within the resist material.
The accuracy and precision with which to fabricate a pattern on a wafer using such a process may be influenced by a variety of parameters. In particular, a lithography process may be affected by parameters of the lithographic tool, such as but not limited to, lens aberration, stage tilt, reticle tilt, exposure dose, and focus. In addition, the lithographic process may be affected by parameters other than those affiliated with the lithographic tool. For example, the chemistry used to etch the topography of the wafer as well as the planarity or thickness of the wafer topography to be patterned may contribute to the qualitative characteristics of the lithographic process. In addition or alternatively, the process parameters associated with the coating and/or bake processes, such as temperature, time, and deposition technique, may contribute to the qualitative nature of the lithography process.
Due to the plurality of process parameters involved within a lithographic process, wafer features may sometimes be fabricated with characteristics outside the specifications of the device. In some cases, the cause of the specification deviation may be determined by examining the history of the lithographic process parameter values and their affect on the outcome of wafer feature characteristics. In particular, reviewing historical data may be used to identify causes of process failure or drift. Such a method, however, may be time consuming, sacrificing the production throughput of the fabrication process. Furthermore, in some cases, the cause of specification deviations may be difficult to determine by simply reviewing historical data, since process parameter value tolerances and dependencies often change with advances in integrated circuit technology as explained in more detail below. As such, in some embodiments, causes of specification deviations may be determined by processing experimental wafers in which one or more process parameter values has been changed. Such a method, however, may also be time consuming as well as costly due to the use of sacrificial test wafers and materials.
In general, a lithography process has two objectives; forming features having dimensions within the design specifications of the device and aligning features within design specifications of the device. Such resolution and alignment goals may be monitored by measuring characteristics of a patterned wafer feature. More specifically, the resolution and alignment of a lithography process may be evaluated by measuring the critical dimensions and overlay variations of a patterned wafer feature, respectively. “Critical dimension” (CD), as used herein, may refer to a dimension of a wafer feature which is deemed to affect the functionality of a device formed therefrom. “Overlay variation,” on the other hand, may refer to the amount a wafer feature is arranged away from its intended position on the wafer.
As stated above, several process parameters may affect a lithographic process. In some cases, certain parameters may primarily affect the critical dimension of a patterned wafer feature while other parameters may primarily affect the overlay variation of the patterned wafer feature. Such an embodiment may be particularly true for the fabrication of integrated circuits having a minimum critical dimension greater than approximately 0.25 microns. In any case, conventional techniques for determining process parameter values and/or correcting wafer feature specification deviations for a lithographic process typically include two distinct and separate analyses; one analyzing the affect of process parameter values on critical dimension and the other analyzing the affect of process parameter values on overlay variation. In other words, no correlation is made between process parameter values affecting both the critical dimensions and overlay variations of a fabricated wafer.
As dimensions of wafer features continue to decrease with the advancement of integrated circuit technology, however, process parameter values of lithographic processes may affect both critical dimensions as well as overlay variations of the wafer features. For example, in some cases, a change in a process parameter value may benefit one measurement characteristic while adversely affecting the other measurement characteristic. For instance, as the tolerance for critical dimension error decreases, variation in process parameter values which only previously affected overlay variation, may also affect critical dimension and vice versa. In yet other embodiments, critical dimension errors and overlay variation errors may collectively contribute to the degradation of an integrated circuit. In particular, even though the critical dimension and overlay variation measurements may be acceptable when analyzed independently, their values may collectively produce a circuit which does not meet the specifications of the circuit design. Consequently, the conventional technique of separately analyzing the affect of process parameter values with respect to critical dimension and overlay variation may not generate an accumulative set of process parameters which produces a wafer feature within the design specifications of the device.
As such, it would be advantageous to develop a method and carrier medium which could collectively analyze critical dimension and overlay variation effects of process parameter changes. More specifically, it would be beneficial to develop a method and carrier medium which would generate a single set of process parameter values which could correct overlay variation error as well as critical dimension error. In addition or alternatively, it would be advantageous to develop a method and carrier medium which would be able to generate a list of potential causes of specification deviations within a wafer fabricated from a lithographic process in a timely and cost efficient manner.